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How to add delay in CPLD?

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harpoon

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delay in cpld

Hi!

I am newbie in CPLD, so excuse me for strange question.

I need to add small delay in MAX7000S output - near 50-60 nS. There are no clock logic there in my project. I was trying to add chain of simple elements - pairs of invertors, but seems compiler is deleting them during compilation/optimization.

I am using MAX+plus II for EPM7064 chip. Working in Graphic editor.

Is there a trick to add small nonclocked delay in some outputs?

I was setting "Global Project Logic Synthesis" to WYSIWYG mode but without success.

Thanks in advance!
 

you can check EPM7064 chip how much time its basic logic circuits delay.
and then you can delay several logic circuits to obtain your requirements.
 

it may be using sample skill
 

Hi Harpoon,
you will have to make sure you are using preserve or keep statements so your compiler does not get optimized them.
The only problem is you want a too small tolerance for the delaytime. You will get problems with jitter, varies with temp/Vcc. Because of all it is recommend that you use an external clock.

Klaus
 

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