harpoon
Full Member level 2
delay in cpld
Hi!
I am newbie in CPLD, so excuse me for strange question.
I need to add small delay in MAX7000S output - near 50-60 nS. There are no clock logic there in my project. I was trying to add chain of simple elements - pairs of invertors, but seems compiler is deleting them during compilation/optimization.
I am using MAX+plus II for EPM7064 chip. Working in Graphic editor.
Is there a trick to add small nonclocked delay in some outputs?
I was setting "Global Project Logic Synthesis" to WYSIWYG mode but without success.
Thanks in advance!
Hi!
I am newbie in CPLD, so excuse me for strange question.
I need to add small delay in MAX7000S output - near 50-60 nS. There are no clock logic there in my project. I was trying to add chain of simple elements - pairs of invertors, but seems compiler is deleting them during compilation/optimization.
I am using MAX+plus II for EPM7064 chip. Working in Graphic editor.
Is there a trick to add small nonclocked delay in some outputs?
I was setting "Global Project Logic Synthesis" to WYSIWYG mode but without success.
Thanks in advance!