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Hi!
I am starting a DVI Board design. The purpose is to generate DVI data in an FPGA. interface it to an DVI transmitter from silicon image. There are quite a lot of data formats to support with dvi. a list is shown below. my question is ho to generate this pixel clocks, ranging from 52MHz to...
xilinx lattice
HI!
I am planning to interconnect a
xilinx RocketIO 2.5Gbps, with a
lattice ECP2M Serdes 2.5Gbps
the serial link should use a light weight protocol for simple data streaming, (or packets with a constant rate).
has anybody ideas on an efficient low resource protocol? could...
HI!
my FPGA project is stuck by having a malfunctioning mpeg2 decoder core. If anyone has a working core for simple profile @ main level, or simple profile @ high level you should contact me, (fast).
regards
hans
We are using X2VP4, X2VP7, and X2VP50s. We encountered severe problems when downloading to the bigger FPGA X2VP50.
The problem is with ise 6.2.03i that the done pin never goes high. With ise 6.2.02i the download works (done pin goes high), but the FPGA cannot get loaded twice. Means I have to...
vhdl insert block
Try using
vhd block:
write your user block in vhd. import it with "Create Import Peripheral Wizard" that is shipped with EDK. Thuis tool generates the necessary file structure that EDK can find it with the "edit cores" dialog.
OPB peripheral:
Create Import Peripheral Wizard...
Hello All!
I am about to begin a design where a stable 48kHz signal should be generated from a PAL video sync signal.
PAL offers several extractable frequencies chipsets as 50Hz, 15.625kHz,...
The 48kHz should be used as a reference signal for AES/EBU audio.
Are there chips(ets) that can...
adpll main design difficulty
I am about to implement an vhdl ADPLL in the next weeks.
i found a good explanation about adplls at:
http://www.aicdesign.org/2003%20PLL%20Slides/L050-ADPLLs-2UP(9_1_03).pdf
example adpll code can be found at:
**broken link removed**
if you find out how good or...
xilnet
Hi,
does anybody have experience with UDP(TCP/IP) stacks available for Virtex2Pro FPGA? Is the XilNet solution available in EDK a good solution?
Are there any reference designs out there incorporating a
Ethernet MAC (EMACLite, EMAC or Opencore EthMac?) and
a UDP stack?
And how the ...
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