Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by guru hegde

  1. G

    combining group of signals in verilog to form like structure

    yeah..it didn't occur to me..:grin:thanks a lot.
  2. G

    combining group of signals in verilog to form like structure

    Hi, I have a group of incoming signals with different bit width belonging to single transaction. I have to store all these inside FIFO or buffer and forward all these to different block.I am coding in verilog. Is there any way to do this without creating individual queue for each signal...
  3. G

    Amba axi4

    Hi everyone I am planning to do project on AMBA AXI4. I have the idea of designing multi master system. I don't know how to go ahead. I welcome any suggestions regarding this. Please give some thoughts.

Part and Inventory Search

Back
Top