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I designed a 2.5GHz CMOS VCO,(core current: 20mA), Rout=300omhs, 3.3V VDD supply, Now core output amplitude is 1~5V. phase noise simulation is about -116dBc/Hz, test is only about -108, the layout, power line:-?, bond wire may all have problems. But now i want to know if 1~5V amplitude is too...
I designed a PLL circuit at 5GHz and 10MHZ pfd frequency as ref. In PLL output phase noise spectrum,a spur at 5MHz offset is found，higher than 10MHz offset，where is it come from？
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