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Recent content by granjan

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    can I instantiate Verilog-AMS module in VHDL architecture...

    can I instantiate Verilog-AMS module in VHDL architecture...:?::???:
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    analoglib vpwl what is delay time and dc voltage

    In analoglib .for pwl what is the dc voltage and delay time fields. Suppose my pwl is defined as below. DC voltage 1.2 v Number of Pairs of points 2 time1 0 s voltage1 6v time2 1 n s voltage2 6v delay time 10n s What does 10 ns delay mean.....Is it the initial time when the waveform...
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    [SOLVED] VHDL simulation in Cadence

    Hi , I just wanted to know what are the different simulation and compilation options for VHDL files...how to compile vhdl file using ncvhdl and do we need to create work library for vhdl file compilation.I'm new to vhdl.. any help is appreciated....:???::???:
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