Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
the model is right.
when you input a "z" to dff, in general the model should output "x".
your design should avoid this case, that means you should give all the input of dffs in your design a certain value.
especially, take care about the memory output to your logic when it has not bus holder,
any dff whih has a transition of "1" to "0" or " o" to "1" consume dynamic power. and the dynamic power consumption is the most important part of cmos circuit.
"0"to"0 does not consume dynamic power but static,
which occupies less compared to dynamic!
you can also insert clock gating yourself!
for exaple: system_clock = clock & en;
when en becomes low, the system will hold current state, because no clock is provided!
Which one is better?
as i understand, the people who design digital circuit
uses analog circuit.that means digital desigers care more about the application of analog not the design of it!
the same explain to the second words.
synthesize question:
i have a design composed of several modules,
and some modules are modified, when synthisize it with the same script, i found
the areas of the modules which i did not modify changed!!!
why???
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
