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Recent content by go4sandesh_vsn

  1. go4sandesh_vsn

    Take your files anywhere !!!

    TYFany (pronounced Tiffany) allows you to take your files along with their hierarchy on a portable storage media (like USB) to be accessed on the run. Any changes in the hierarchy on the portable media can be docked with the base hierarchy...
  2. go4sandesh_vsn

    LVDS Serialaization Factor

    hi I was going through a document on an LVDS interface which says the serialization factor is 8:1 (or interface works at 8:1 serialization , it's a 16 channel LVDS). But I couldnt get what does it mean ? Can someone explain its significance... thnx a lot
  3. go4sandesh_vsn

    Which one is more preferred BGA or TSOP?

    hi.... can someone tell me which one out of BGA n TSOP is more preffered n why.... as far as i know its BGA....but can u compare in terms of onchip soldering or placement complexities on the PCB.... thnx in advance
  4. go4sandesh_vsn

    Which SelectMAP mode to choose?

    hi everyone.... there r two SelectMAP modes namely 1) Slave SelectMAP 2) Master selectMAP can someone tell me....which one of them is more preferred and why????
  5. go4sandesh_vsn

    Is there a way to convert a HDL code to schematic?

    a basic question so tht means lotz n lotz of work 4 someone who does the schematic compared 2 the one who does RTL coding(HDLs).... thnx
  6. go4sandesh_vsn

    Is there a way to convert a HDL code to schematic?

    hi eveyone i m very new to this field ... went thru some tutorials....but little confused in the basic PCB design FLOW.... as it says we start from the schematic....so does tht mean we hav to ourself create the entire schematic...(in case for a bigger module i suppose thts going to b difficult...
  7. go4sandesh_vsn

    Help needed for the LUT based time delay code

    wat's tht ckt supposed to do???
  8. go4sandesh_vsn

    Mixed Simulation of Design (VHDL and Verilog)

    vcs vhdl verilog mixed simulation whichever simulation tool u r using...make sure if it supports mixed HDLs (nowadays most of them do).....n just follow its related documentation..... particularly for Modelsim, u can follow its "modelsim_user.pdf" file ...it has an entire chapter dedicated to...
  9. go4sandesh_vsn

    How to calculate the depth of FIFO and what are the designs contraints for it?

    depth of fifo its simple...burst data means one or more data access at a time.....or in a better way u can take an example as: if u give command a memory controller to feed u with next FOUR data (in the next say four clock cycles) starting from some particular memory location ...then we say u r...
  10. go4sandesh_vsn

    Can't find the xilinx.pga.pin file for PIC setup

    hi.... in PIC setup...xilinx.pga.pin file is required..... but i dint find it anywhere on my comp....i think it wasnt there in my Xilinx installation.....did anyone face such probs.....wat cud b the probable cause....tell me if any downloads r available
  11. go4sandesh_vsn

    wat does 65nm 90nm mean

    hey ...in some of the above posts...ppl saying ....65 nm is "HALF" the channel length(i.e equal to Feature size)....whereas some saying its the channel length(tht means must be twice the Feature size)...... can someone clarify....watz the actual answer...as far as i m aware its the Lmin n not...
  12. go4sandesh_vsn

    footprint compatibility

    hi...can anyone tell me what do we mean by footprint of an FPGA...? n its said tht Virtex5 devices are footprint compatible...what does it mean?
  13. go4sandesh_vsn

    Anybody can share Xilinx Training documents?

    xilinx global timing constraints tutorial .pdf can anybody share xilinx training material for virtex 5 "Designing with the Virtex-5 LX"
  14. go4sandesh_vsn

    Can I use the Xilinx's vendor ID for the PCI interafce?

    PCI vendor ID yes ur card's vendor ID will be the same as xilinx's vendor ID ie 0x10EE... device ID can be watever u wish...abt subvendor ID, i think most of the time its not required ...or may b can use it if u hav some chips from some other vendors as well....
  15. go4sandesh_vsn

    integrating blackbox to VHDL project.

    if its solved ...just tell me wat do u think was the problem...n how it was solved
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