Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by gnvelkumar

  1. G

    LTspice 'don't know how to detect this circuits steady state'

    Hi, you tried with initialize some node voltage?. if not try , because LT spice do DC analysis(internal) before AC
  2. G

    Lib files for tanner .model .md

    Where can I get model libraries
  3. G

    [SOLVED] Model Library Files for Tanner EDA

    hi Where can I get model any librarie if u get let me know
  4. G

    hi i am trying to simulate invertor in s-edit of tanner......

    Dear All, I where I can get .lib file for tanner. I am not having any library files with .lib extention.. but I am have some model files for nmos and pmos with .md extention.. I dont knw how to invoke library any one can help me
  5. G

    How to design AND Gate using one pMOS and one nMOS

    How to design AND Gate using one pMOS and one nMOS?
  6. G

    Computer aided design for vlsi

    After designing new circuit , that must be converted in to layout for implement on Silicon wafer. so every code first converted in to netlist (circuit in terms of delays and wire) then layout , for Layout design we must go with Physical design tools(CAD tools) like cadance SOC encounter for...
  7. G

    [Moved] Help Me to get JOb in VLSI field

    I am Velkumar, completed M.E VLSI Design in RMK Engineering College, Chennai. and secured First mark in M.E with aggregate of 8.8 CGPA. I have worked in DRDO as a trainee for SATA IP Core Development using Verilog HDL. I have hands on experience in EDA tools such as Cadence- Virtuoso, RTL...

Part and Inventory Search

Back
Top