Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by glinsana

  1. G

    why vth shifts wrong when L gets smaller in Cadence ADE

    Vth gets bigger…… by which i mean |Vth| - - - Updated - - - I take them into consideration too. But the results i got yesterday by Id-Vgs DC sweep test brings a result that proves |Vth| should get smaller when L gets smaller.I think it is the right "short channel effect",isn't it? :-)
  2. G

    why vth shifts wrong when L gets smaller in Cadence ADE

    hi,guys i am really confused about Vth right now here is my story I have an pmos, it's model is from SMIC 0.13um and use BSIM3v3, Cadence ADE,spectre for simulation I choose to save DC operating point in order to save vth for my pmos but I found when L gets smaller, vth gets bigger...

Part and Inventory Search

Back
Top