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Recent content by gl.a

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    Clock output from FPGA

    I tried to instantiate and set up the DCM manually: DCM_CLKGEN_inst : DCM_CLKGEN generic map ( CLKFXDV_DIVIDE => 2, -- CLKFXDV divide value (2, 4, 8, 16, 32) CLKFX_DIVIDE => 1, -- Divide value - D - (1-256) CLKFX_MD_MAX => 0.0, -- Specify maximum M/D ratio for timing anlysis CLKFX_MULTIPLY...
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    Clock output from FPGA

    Thank you for your answer but, i tried both, as you write too and if i negate there, i got a different warning and it's still not working: Actual for formal port c1 is neither a static name nor a globally static expression:grin:
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    Clock output from FPGA

    I have read it, but i'm still confused. (i lurked every similar topic, and i read the official xilinx primitive usage guide) Could you explain it to me? Or maybe it's better if i sleep on it. I'm guessing i do a silly mistake.
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    Clock output from FPGA

    Hello! Thak you for this information, i have the same problem. I am still having it because it allows to implement but there is no clock on Q aka the output of the ODDR2. I have a warning: Xst:2016 - Found a loop when searching source clock on port 'i2s_mclk_in_neg:i2s_mclk_in_neg' My...
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    Piezo + Nexys 3 connection

    Hello! What is the safest way to connect a piezo to the Nexys 3 PMOD? Trough a transistor? Or could i connect it directly? Thanks.
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    how pcie works in fpga

    For PCI communication, there's a very nice tutorial on https://www.fpga4fun.com/. I suggest you to read after the PCI frame, understand it in detail. Design an FSM(finite state machine) on paper and after that you can code it in VHDL, Verilog or what you like. Good Luck!
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