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That would be nice.
I must admit that my knowledge of PCI is not so great.
The code I uploaded is only the code of the test application delivered by Xilinx.
But I presume it's in that file that I have to integrate the "gateway_in" and "gateway_out" of the algorithm along with the interrupts,... ?
Ok, I hope this version will be less vague :)
I want to send a video file from a pc to a FPGA (on a XUPV2P development
board) via the PCI interface. On the FPGA the video will be processed by an
algorithm. The result, after processing, will be send back to the pc. I
generated the VHDL-code of...
Hello,
I have a XUPV2 Development Board with a Virtex-2 Pro XC2VP30 FPGA.
The manual says that it supports a USB 2.0 connection.
But when I plug it in on my PC, the message appears that it can work faster and it registrates only a USB 1 hardware device. Other hardware on my PC works well with...
Wrapper
Hi,
I need to send data from a PC via PCI to the FPGA, where the data will be processed (videoprocessing-algorithm), and then sent the result to the PC via PCI.
I already generated the VHDL-code of the algorithm with "Xilinx System Generator" and also have the VHDL-code of the...
xilinx system generator
Hi,
Can someone tell me how I can get an image through the "gateway in" of the xilinx system generator set?
I use the "image from file" block from Simulink but ofcourse it gives a matrix. So how can I convert it to a sysgen usable thing?
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