Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Re: SNR calculation in Sigma-delta modulator
Reza , are you sure that A is the amplitude of the input signal and not the quantization step , Why should increasing input amplitude decrease SNR ?
Can you quote the textbook ?
Can you show calcultations ?
You are surely going to loose some benefits of Differential Output ,
1- PSSR will be bad because the DC part output ( which is now a signal instead of output CM ) will change with fluctuation in current source of I/2 due to supply noise
2- The CMRR will also be effected to a...
Hi oldsamples , Would you mind sharing the structure you are simulating , How are you coupling the input to the resonator , Do you expect 50ohms input impedance from resonator at resonance ( that seems to be the case as you expect S11 to dip) , If the loss component of the resonator is very...
Hi Santosh ,
What is your target platform , FPGA , ASIC or just Verilog Simulation .
Do you have timing constraints that you have to do this in one clock cycle .
Barrel Shiftier is a combinational circuit which produces a shifted version of the input according to the shift code , and for...
For Setup time specification to be met , data has to reach the flip flop input Ts time before Clock Arrival , If clock gets delayed by some amount ,data can also tolerate the extra delay , the worst case for setup will occur when clock is right at time ( Minimum dELAY ) and data is as late as...
heya Sj95
Let me elaborate a bit on what LvW already said ,
To understand the physical meaning let us first agree that we are giving a sinusoidal input to the system say Asinwt and measuring the amplitude and phase shift the output say B(w).sin(wt + Phi(w) )
->Clearly the gain is...
Heya paddy_p,
Another problem can arise from the way you have lay out your circuit , For example if you have done it on a bread board and the wires near to the Interrupt wires are switching , In worst case you can assume that there are two wires near to the Interrupt wire that are...
The concept of 90deg phase is valid only when you are talking about a sinusoidal input system and that too once it has reached the steady state , SO the only truth here is that In a system where the voltage across a capacitor is given by Vsinwt , the current in it will be Vsinwt/Xc =...
I did not quite understand why transient simulation should be a problem , you can create a clock source in spice , you can then either instantiate a counter model or construct a simple counter from FF's , You can then connect counter outputs to ideal switches / Mos switches as your wish . I do...
Re: PSSR
hrkhari , Power Supply Noise is not really a 'Common-Mode Noise ' , in the sense it is not a noise common to both the inputs of a differential Amplifier , To analyze the PSRR of an opamp you need to consider two cases , Noise on VDD and Noise on VSS , in each case the small...
grit_fire , I found the solution to this after much head breaking , here concentrate on the word "reference plane " , Ports having same reference plane means that they either have the same X co-ordinate or the same Y co-ordinate , You should see only one white line and not two which ADS draws...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
