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In general the soluciont is to reduce capacitance, reduce resistence resistence or increse the current capability of the driver, this is don by:
Resize the source gate (increase the current capability, be careful with electromigration)
Redude fanout (reduce the capacitance)
Add...
First you must insert your MBist after this, before you insert the boundary scan you mus decalre the new instruction for the TAP and the declaration of the Data Register asociated for the Tap instruction. (in the Data Register you add de activation, status and other functions you need for you...
have you tried verify the existence of the 3 basic libraries: WC, NC and BC (Worst, normal and Best case). Those are PVT (process, voltage and temperature) variants of the same library and your vendor must provide it.
I don't remember the commands for astro. You can have a good help if access...
simulation vcd dumpvars
I use a littler bit of Astro Rail for power analysis, is good for this task but I used it just for digital analysis. All the analog section was implemented as a hard macro with a model for the power and switching.
Re: scan chain help
You can assign an IO port in a shared function (Scan_in and data_in or Scan_out and data_out) just indicating the start and end point of a chain. If you don't do this the DFT compiler will create the specific pins for Scan_in and Scan_out. Also if you have a constraint for...
Re: rom, ram power connect
If you have a complex design and it generates a lot of noise you can put the memory in a different power ring.
If your design have an analog block and a memory block is high recommend to isolate the analog from the rest of the circuit (it means the memories can be...
The power for the core and pads are made by the diferents rings in the power pads. You must use pads with the corrensponding rings (i.e. IO65_33 or IO65_18, it depends of your librarys, Vdd18, Vdd33).
When you are conecting the power straps and rails dont forget to asign it to the correct net...
Re: DFT help
The constraints of length of a chain is not a prioritity constraint. If you have low coverage check for Testability issues for example:
Not reset controlability.
Clock gatting
Clock domains
Latches
If you avoid this problems your coverage will increase.
All...
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