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Recent content by gaoyanli

  1. G

    assura lvs and lvs for rcx

    as we all know, before run rcx we need lvs clean, and run rcx need to read the file lvs created. could you please tell me whether you run normal lvs or special lvs for rcx(different setting, extract rule from normal lvs), and if you run special lvs for rcx, could you pls tell me why?
  2. G

    can vxl help in a higher hierarchy

    it's the first time for me to use vxl in project, and I feel when it works in transister level or gate level it helps a lot, but when the hierarchy getting higher, it's more convenient to work in vle, do you feel the same thing, may I swich between vxl and vle very often?
  3. G

    simple layout question

    m1_nwell cont should be placed inside nwell. for example if you work in p-sub tech,always place con-wn in nwell and con-sub in sub as many as posible, to make nwell and sub connect to vcc and gnd very good!
  4. G

    What is the best layout editor?

    virtuoso vxl ( with some bugs exist and some constrains but useful)

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