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Re: layout in ADS
@DDavid.......yes i want silicon layout ....
plzz refer to this post fr detail of the schematic
Added after 2 minutes:
@mikekan,wireless man.......i dont have access to cadence i have only ads with me........ if it is not possible plzz tell me some layout available for...
layout in ADS
I have designed and simulated a wideband LNA using CMOS 0.18um TSMC technology.........i want to draw a layout fr this circuit using ADS and measure the chip area it takes...can this be done? also is LVS possible in ADS?...........can anyone please help me regarding...
wide band lna design
hey Tyassin that document was really of great help................thnxs a lot................... please help me regarding how to draw layout of the above ckt using ADS....
wide band lna design
Hi Tyassin,
I got gain of around 12.5 db over the intrested frequency range......i increased the value of resistor in the o/p stage bt the return loss is still of concern....
Added after 1 minutes:
can nyone plz tell me hw to measure iip3 for the wideband lna using ads
lna design proper
thts great dude atleast u r getting positive gain......i ws trying tht fr last afew days................can u please send me the schematic file.......or mail on ganesh634@gmail.com
lna design+design procedure
@tyassin, Abhishekabs.......i am attaching the schematic, s-parameters and noise figure graph with this post......plzz let me knw wat the changes to be made to get proper s-aprametes and noise figure
I am designing WB lna fr freq rand 3.1 Gz to 10 ghz, m using ads fr simulation of schematic......i am getting proper frequecy response for S21 plot bt the gain is negative can ny1 tell wat is the problem..............immediate help is appreciated........
also can ny1 tell me hw to draw layout...
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