Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Is this something related with replication, when a net is split, driven by multiple buffers, each buffer will drive a low amount of destinations, reducing the net loading ?
gab
Designing with FPGAs ?,
or designing an FPGA silicon?,
For design with FPGA, I think it's more than enough what you find on Xilinx and Altera websites. I don't think what else more useful you can find in FPGA books, anyway any FPGA book is already to old.
gab
1.) Generate for each Designware component a gate level netlist, with Synopsys DC.
2.) Remove all Designware components modules from Synplify ASIC project, and declare them Black Boxes
3.) Use multiple EDIFs for Place&Route
gab
thanks for reply,
Yes I know, but why a brand new first tool release on linux will choose 6.x
when 7.x was already available on the
release date ?,
Because all other tools are on 6.x ?
thanks
gab
I had the same problem, years ago ...
Try to find Power Resistors made from a resistive wire that you can solder ...,
and use that wire for buiding new
resitor values.
gab
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
