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Recent content by FR1985

  1. F

    how to make a testbench for an UART

    hi every one i want to make a test bench for an UART on verilog but i dont know how to start cause iam new on verilog programming that why i need a help. these is the code of the UART which i want to test:i want to introduce a data in :i_uart_tx_data and check if i got the same data in the...
  2. F

    difference between Native interface FIFOs and AXI4 Interface FIFOs

    thank so much for your help
  3. F

    difference between Native interface FIFOs and AXI4 Interface FIFOs

    thank you very much for me i need to use it with a ddr controller so i have to choose the AXI4. can you tell me when we have to use the native fifo? i really appreciate your help thank you again
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    difference between Native interface FIFOs and AXI4 Interface FIFOs

    yes you have write, i have read before this documentation and i still not knowing when we have to choose to use NATIVE FIFO and AXI4 . as you said that AXI4 is derived from NATIVE FIFO, can you tell me when i have to choose NATIVE FIFO or AXI4 THANK YOU
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    difference between Native interface FIFOs and AXI4 Interface FIFOs

    Hi every one The Xilinx FIFO Generator core supports Native interface FIFOs and AXI4 Interface FIFOs Can you explain me the difference between these two interfaces thank you
  6. F

    the use of the IP CORE GENERATOR

    hI every one can you explain me the reason of the use of the IP CORE GENERATOR . i dont kwow when we can use the IP CORE GENERATOR Thank you
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    difference between FIFO and FWFT

    thank you very much for your explanation.
  8. F

    difference between FIFO and FWFT

    hi every one can you explain me what is the difference between First In First Out FIFO and First Word Fall Through FWFT thank you
  9. F

    Differences : MMCM vs PLL vs DCM

    Hi can you explain me the difference between MMCM and MMCM_ADV and MMCM_DRP thank you
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    Usage of non blocking assignments in verilog .....

    thank you very much for your explanation
  11. F

    Usage of non blocking assignments in verilog .....

    hi can you tell what mean this instruction: mem[wr_addr] <= i_data; why we use mem and inside another reg thank you
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