how to make a testbench for an UART

[FR1985]

hi every one
i want to make a test bench for an UART on verilog but i dont know how to start cause iam new on verilog programming that why i need a help.
these is the code of the UART which i want to test:i want to introduce a data in :i_uart_tx_data and check if i got the same data in the output( o_uart_rx_data). dont hesitate to give me some advices

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Code Verilog - [expand]
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module TB_UART;
 
    // Inputs
    reg clk;
    reg i_rst;
    reg i_rx_data;
    reg i_uart_tx_en;
    reg [7:0] i_uart_tx_data;
 
    // Outputs
    wire o_tx_data;
    wire [7:0] o_uart_rx_data;
    wire o_uart_rx_data_valid;
    wire o_uart_tx_buffer_full;
 
    // Instantiate the Unit Under Test (UUT)
    uart_top uut (
        .clk(clk), 
        .i_rst(i_rst), 
        .i_rx_data(i_rx_data), 
        .o_tx_data(o_tx_data), 
        .i_uart_tx_en(i_uart_tx_en), 
        .i_uart_tx_data(i_uart_tx_data), 
        .o_uart_rx_data(o_uart_rx_data), 
        .o_uart_rx_data_valid(o_uart_rx_data_valid), 
        .o_uart_tx_buffer_full(o_uart_tx_buffer_full)
    );
 
    initial begin
        // Initialize Inputs
         clk=0;
        i_rst = 0;
        i_rx_data = 0;
        i_uart_tx_en = 0;
        i_uart_tx_data = 0;
 
        // Wait 100 ns for global reset to finish
        
        // Add stimulus here
                
end     
endmodule

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