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read_vcd command in primetime
Hello !
I have exactly the same issue :cry:. What is the cause, the consequence and how to get rid of those warnings ?
Thanks for any help,
Flyjuju
Allright, I'm back and still with some hold violations !
So I tried Pont de Pedra proposals, especially the clock specifications and it solved a lot of the violations. I didn't apply any multicycle constraints because I'v heard that it had some functionnal consequences. Thanks a lot for the...
I actually have many setup time violations and hold time violations (more than 200). I guess that the problem comes from the fact I use an integrated PLL (altclklock function) provided by altera for APEX boards (I use this in order to multiply the original clock by 3, to 'sample' an incoming...
Hi !
I'm currently performing an implementation on an FPGA with Quartus II and I have a problem with timing analysis relating to setup time, hold time and negative slack. I would have liked to know CONCRETELY what actions I have to take in order to solve this because I know absolutely nothing...
Hello everybody !
I have a project to realize, i.e. the connection of many FPGA (board Altera APEX 20KE) into a Network-on-Chip. The main issue I have is that the has a frequency of 33.333MHz with a precision of +- 1ppm.
So, when I send informations (serially) between 2 FPGA, I have absolutely...
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