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Recent content by firegun

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    Hi,I have a problem about how to use a model include subcirc

    Hi,rfsystem!Your answer helps me a lot.But I still have a little puzzle.Do you mean I just need to fill the subcircuit name in the modelName blank?Please show me the way!Thank you!
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    Hi,I have a problem about how to use a model include subcirc

    I use spectre to simulate a RF like circuit.
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    Hi,I have a problem about how to use a model include subcirc

    inline subckt hspice I have a model file with subcircuit defined in it.But I cannot simulate my circuit when I fill the subcircuit name in the blank of modelName.And I have to invoke the features of the subcircuit!How can I solve the problem!Please help me!Thanks! Posted from a mobile
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    Generate netlist from layout!!

    Do you wanna run a post simulation to ensure that your layout could work correctly with the parasitical risistors or capacitors?Maybe you should use the LPE and PRE tools to get a full netlist for your simulation. Send via mobile phone wap.edaboard.com
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    The difference between Pmos and Nmos when they act as a TG

    Re: Help!A basic question! Thanks,v_c! The documents show me much help!
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    The difference between Pmos and Nmos when they act as a TG

    Help!A basic question! Hi friends! I am a rookie.Now I have a question!Pls help me! I want to know the difference between Pmos and Nmos when they act as a TG.And what's the benefit of using a cmos TG? Thanks a lot![/code]
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    The difficulty of selecting nMOS size on ESD

    I think you can decrease the L,while you should add a little resistor between the Output Buffer and ESD devices.
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    Co-simulation of Analog & Digital cells

    You can use the SpectreVerilog option to simulate your circuit.I think that can help you.You should create a .config file in your circuit view first.

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