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I'm disigning a classic socond order sigma-delta modulator(CIFB structure), wiht osr=128, fs=64K,ENOB=13bits. How to determine the op gain for the first integrators?
Should the dc error at the output of the first integrators should be smaller than 1/2 LSB?
Or we can other ristrictions to...
In the verilog-a model, use voltage-control-voltage source to model the opamp, the gain is 2000, offset and saturation are not concerned.
The simulation time is long, due the accumalted error is so large, that the verilog-a model shows a diffence from the matlab model.
This maybe the point...
After voltage scalling, the output swing of integrator in SDM using verilog-a model is different from the SDM model using Matlab model, how would this happen?
I am a new comer to Sigma-Delta Modulator.
Now I working on a two order SDM, ENOB=13bit
Fist I do ideal simulation in Matlab, and find the output swing of integrator is -3v~+3v
But 3.3v transistors are used in our design, does this means the design in Matlab is improper, I have to choose a...
low voltage self-biasing reference circuits
There are three state for the circuit:
1,0, and bi-stable state
when the clk is high, the self biasing circuit(regenerative circuit) strives out of the former 1 or 0 state, Vout+ and Vout- settle down to the same voltage( at least very closely...
triple well cmos process
Tripple would provide much better LATCH-UP protection over the TWIN well structure.Usually a extra deep N well is implemented underlying the P-Well or N-well, the minority carriers is collected by the reverse biased local (bulk-to-deep N well) junction.
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