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Ya, unfortunately when stupid people use a cost model they don't understand, you get stupid results. Of course, it doesn't help if the model itself is poorly designed. I'll try to get that part right. And i'll try to make sure it doesn't get used to swamp the engineers with BS meetings and...
Haha thats not the first time i've heard that Ice-Tea :) Must be true. Hope you guys had a great Thanksgiving!
For that scale of 1 to 10 I talked about....
What's a realistic range that 90% of projects would fit into? 2 to 9? 4 to 8? 1 to 5?
I would guess I need different ranges...
Thanks TrickyDicky.
So the effect of design reuse depends on how easy it is to link the IP together into something that works for your project. For IP that is a perfect fit for your design, it could reduce stage 1,2 costs to near 0. For IP that is difficult to link together, has bad...
Thanks for the response.
So if I understand the scenario you described - you have exactly 100% IP reuse, 0% new design. The effort for the project was
Preliminary Design: 0 days, 0%
Detailed Design: 0 days, 0% of the total
Implementation: 4 months effort, 100% of the total
Now consider...
Hi Everyone,
I'm a cost model builder and an FPGA newb, and i've been tasked with designing a quick, high-level, early stage FPGA cost model. I was hoping you guys could help me out.
The model has 3 activities
1. Architectural Design (high-level design/architecture work, behavioral HDL...
Hey Guys,
It's been a month since I last posted. I've found alot of people suggesting VHDL lines of code as a good sizing metric for the entire development effort, from requirements defintion all the way through testing. I hear that many designers have a good feel for how many lines of code a...
OK, with all the reading i've been doing and with your crucial help, i'm starting to get a clearer picture of how this works.
Just to be clear, for my project I absolutely have to come up with SOMETHING that will convert active logic cells into a reasonable (not perfect) gate count. I can also...
Thanks for your replies, they were very helpful.
So it seems that an ASIC gate is a pretty good sizing metric. 100 gates in "design A" is roughly equivalent to 100 ASIC gates in "design B"
The only reason design A would take more time than to implement than design B is that one is more...
Hi Everyone,
I'm quite new to FPGA development, and I was hoping you guys could help me out. I've been given a project to take an old ASIC development/production cost model, and adapt it to estimate FPGA costs. I've done some basic research, but I still have many questions.
1. My first main...
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