Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Please answer the following question if it is clear.
I am using Altera FPGA board for saving a snapshot to a frame buffer and to send it serially to Matlab. My problem is that all the parts of my code are right but the received data to Matlab code are 14 bits rather than 8 bits.
I tested each...
By following the steps available in this website https://www.youtube.com/watch?v=nHFVwthr_Ew, it becomes easier to define the serial port. But what is the step after compiling to Nios? And is it necessary to open Nios whenever board programming is needed?
Hello,
I wrote this code for clock division from 921600Hz to 115200Hz, but something is going wrong. Can anyone help me?
module step1_divider (
input clki,
input reset,
output reg clkf
);
localparam constantNumber = 4'b1000;
reg [3:0] count;
always @ (posedge(clki) or posedge(reset))
begin...
Hello,
I have pixels (12 bits each) and i need to send them serially by UART RS-232 while the maximum data bit is 9 bits. How can i send the data of each pixel without any compression?
Thanks
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.