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Hi,
I have an LNA with this schematic:
and I inserted 2 frequencies to the input port and plotted the available gain with SP simulation:
then based on the curve for gain, I changed the two freq to 3.1GHz and 3.2GHz:
and then I had these set up for plotting IP3:
My question is why is it that...
Hi,
I'm new to ADS. Can anyone tell me if a plot in which vds is swept and Id is plotted for different values of vgs, Vdsat be plotted? If so, how is it done??
Thanks in advance
May I ask how you added those other lines like"closed loop stable? " or "PM=70.1"?? because mine doesn't show such information.
Thank you in advance.
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ohoh i should right click and choose the charactristics tht I want to be shown
thanks
Thanks for the time you spent on this! Actually in the book it isn't calculated enough, more the results are shown.
I'd be really thankful if you updated sooner
Thanks for replying,
I am supposed to prove through mathematical relations that if the open loop transfer function of an op-amp has 2 poles in LHP, and one is 3 times larger than the gain bandwidth product, then PM=70 degrees.
Why is it that if the non-dominant pole is 3 times larger than the gain crossover frequency, the phase margin will be about 70 degrees?
is there a book that this is discussed?
The overall circuit is not working it has a PSRR of 8dB , but it must be designed for -70dB PSRR. and the amplifier I used works with 1 volt but I have used it in this bandgap reference which works with 2.7 volts (do both the amp and the BGR need to work with 2.7 volts? ), the bandwidth of the...
Thanks for the reply,
How can I know what restricted common mode range is? so for my amplifier the BJTs better to be in active region and not saturation? for mosfets:
region 1 ---> triode
region 2 ---> sat
what number represents the active region for BJTs ?
I am trying to simulate an opamp for a Band Gap Reference, all the mosfets are in saturation but not the BJTs... can't figure out why... and I only have this npn available in my tsmc18rf library. I am applying 1v as the power supply in vdd and applying 0.6 dc volts to in+ and in- .
and another...
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