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High impedance node in an op-amp

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fateme m

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Why do high impedance nodes in an op-amp create the dominant pole?
 

What maximizes R*C delay? Given that C varies little,
one transistor pair or trio to another?
 

In an IC op amp, capacitors take up a large area so you want to minimize the size of the capacitor used for compensation.
This means you want the capacitor at a high impedance (resistance) node so that, for a given RC time-constant (for the desired roll-off pole), the capacitor is as small as possible.
 
Thanks for the reply,
Dominant pole is the frequency at which gain of the op-amp starts dropping...What is the relationship with RC delay?
 

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