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rising_edge(clk)
Yes you can!
In VHDL every process is a concurrential statement, and your structure on rising edge wakeup processA e on falling edge wakeup Process B
The code is also synthesizable by Xilinx.
verilog gate level simulation in modelsim
I'm using Modelsim 5.7, an I'm tryng to simulate a gate level netlist.
But if i use an implicit wire declaration es. or2 (siga,sigb,out); the simulator don't attach the net to the module output and I find always X.
But i if I check the module itself it...
displaying temperature on lcd
You have to use A/D converter of PIC and implement a conversion table on code based on sensor chart.
for displaying on the lcd screen, i think you have an in-built controller on lcd.
For code you can search in piclist forum at www.piclist.com
Wasted PICs
If the PIC is mounted in circuit you have beep because the capacitors between VDD & VSS.
Out of circuit or if you don't have mounted bypass capacitors the PIC is probably broken.
For programming:
RB7- Data
RB8 - Clock
MCLR- Master clear/VPP
VDD
VSS
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