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Recent content by fant123

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    How to detect High-Z state in VHDL or Verilog?

    verilog high z you can use in VHDL 'h' : if bus='H' then data<='1';
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    both rising_edge(clk) and faling_edge(clk) in one progrm,ok?

    rising_edge(clk) Yes you can! In VHDL every process is a concurrential statement, and your structure on rising edge wakeup processA e on falling edge wakeup Process B The code is also synthesizable by Xilinx.
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    Can anyone provide Synthesis Checklist

    synthesis checklist you can use the SYnopsys checklist
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    Modelsim verilog gate level simulation

    verilog gate level simulation in modelsim I'm using Modelsim 5.7, an I'm tryng to simulate a gate level netlist. But if i use an implicit wire declaration es. or2 (siga,sigb,out); the simulator don't attach the net to the module output and I find always X. But i if I check the module itself it...
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    displaying temperature on LCD

    displaying temperature on lcd You have to use A/D converter of PIC and implement a conversion table on code based on sensor chart. for displaying on the lcd screen, i think you have an in-built controller on lcd. For code you can search in piclist forum at www.piclist.com
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    Whats wrong when multimeter beeps between Vdd & Vss on 8

    Wasted PICs If the PIC is mounted in circuit you have beep because the capacitors between VDD & VSS. Out of circuit or if you don't have mounted bypass capacitors the PIC is probably broken. For programming: RB7- Data RB8 - Clock MCLR- Master clear/VPP VDD VSS
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    Looking for good study book to learn CPLD and FPGA

    learning CPLD and FPGA I think you have to study VHDL before A good book is Perry -VHDL - 2nd edition

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