Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by eses23

  1. E

    Could I apply the linearization techniques for cmos to nonlinear HJFET ?

    There is few linearization techniques has been reported for cmos. But I am wondering that can I use these techniques for other nonlinear fets(e.g. hjfet)?
  2. E

    TMSC cmos parameter download

    How can I download tmsc cmos parameter ? Is is text file or different file format?
  3. E

    Cmos LNA circuit in LNA?

    Cmos LNA Design Example in AWR **broken link removed****broken link removed****broken link removed****broken link removed****broken link removed****broken link removed** I want to analyse with derivative superposition method cmos LNA in AWR. I try to simulate the circuit. But the results are...
  4. E

    Cmos LNA circuit in LNA?

    I try to simulate derivative superposition cmos Lna in AWR circuit . But the results are very odd. I use 0.18um cmos. I biased cmos's in weak and strong inversion values.I showed my circuit and the graphs in these images. Please someone tell me whats wrong?
  5. E

    For cmos LNA building LC tank in AWR

    My Cmos LNA circuit's has an LC tank. I don't know which element should I use for inductor and capacitor. For capacitor can I use varactor? And If I can use a vcap, how can I import the data file of vcap?
  6. E

    For cmos LNA building LC tank in AWR

    Re: Cmos LNA Design Example in AWR Sorry, I wrote these accidentally. S11,S22 and S21 are dB. Do you have any circuit example. If you will give me an example circuit,I can compare with mine.
  7. E

    For cmos LNA building LC tank in AWR

    Re: Cmos LNA Design Example in AWR Sorry, I wrote this informations the previous post. So,I couldn't think that. I used 180nm Cmos process and apply the folded cascode LNA with Mds Technique (modified derivative superposition). The center frequency is 5GHz. I import the spice netlist in Awr...
  8. E

    For cmos LNA building LC tank in AWR

    Cmos LNA Design Example in AWR I want to design a cmos LNA circuit in AWR. I built in AWr and run.But I can't obtain reasonable result. I think I can't choose the right element.Could someone give me an example circuit,Please?
  9. E

    [moved] Cmos LNA Design Example in AWR

    I want to design a cmos LNA circuit in AWR. I built in AWr and run.But I can't obtain reasonable result. I think I can't choose the right element.Could someone give me an example circuit,Please?
  10. E

    180nm Cmos LNA design

    I want to design 180nm cmos LNA in AWR. I have an input and output matching network. Noise figure,input and output matching values are normal but I can't get the reasonable result for the gain. The gain is -3dBm. I am so confused.I can't find the problem.Please help me.
  11. E

    add cmos s and noise parameter in AWR design environment

    I want to add 0.18um cmos in AWR. But I can't find any library or parameters. How can I add any Cmos process in AWR ? Please help :-?
  12. E

    Using s-parameter for simulation in pspice

    I want to find power gain(S21) ,impedance matching (S11) and noise figure using s parameters for cmos LNA.And I want to do simulations in orcad pspice. How can I do that? please help
  13. E

    how can I plot Pout-Pin graphs in orcad pspice?

    I want to plot Pout-Pin graph in pspice. In DC sweep analysis, I can sweep only voltage or current. I can't sweep Pin. So ,I think I can do this with parametric sweep analysis but I don't know how. Please help me, Thanks in advance
See more

Part and Inventory Search

Back
Top