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Recent content by emmagood

  1. E

    Interfacing HEX keypad with FPGA to display output on seven segment display

    I am only using waveform test bench in Xilinx ISE....
  2. E

    Interfacing HEX keypad with FPGA to display output on seven segment display

    As I have understood this, I can input the value of coloumn to be 0111,1011,1101,1110 in the test bench. Then how will one of the rows will get selected and the test bench waveform will show either 0111 or 1011 or 1101 or1110..? Consider doing a dry run of the code pls. Thanks, Emma
  3. E

    Interfacing HEX keypad with FPGA to display output on seven segment display

    No... I dont know how to simulate the code.... I can give the coloumn line inputs but how do I give the mechanical switch input which will short the row and coloumn lines ...Then only I can see the output of the row line vector and thereby decide if the vector for seven segment is getting the...
  4. E

    Interfacing HEX keypad with FPGA to display output on seven segment display

    OK... and how to decide the length of the internal counter...? Also, did you find the code in the previous **broken link removed**OK. Thanks, Emma
  5. E

    Interfacing HEX keypad with FPGA to display output on seven segment display

    Also, to add, the code at **broken link removed** is getting stuck at 2 just after programming and not reading he value of the keys pressed. Thanks, Emma.
  6. E

    Interfacing HEX keypad with FPGA to display output on seven segment display

    Thanks for the reply. I did not know that "after <time duration>" is not synthesizable (I am still learning VHDL). Is there any list of VHDL language constructs which are synthesizable. If so, do point me to the same. Also, for counting clock cycles, how to decide the length of internal...
  7. E

    Interfacing HEX keypad with FPGA to display output on seven segment display

    ok...I have typed the code and sketched the keypad diagram. The problem is that the seven seg display is getting stuck at 0 just after programming and not taking any other value from the keypad. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use...
  8. E

    Interfacing HEX keypad with FPGA to display output on seven segment display

    :D Well I also tried to google for a sample code and got several codes. But I was unable to understand them. The lab PC is isolated (does not have internet / open USB ports). Hence not able to post the code here.
  9. E

    Interfacing HEX keypad with FPGA to display output on seven segment display

    Hi there, I am trying to interface a HEX keypad with to display the key pressed on seven segment display. I am new to HEX keypads. I have read some theory about HEX keypads. But I am unable to make the decoder. Can anyone pls provide a sample code for it in VHDL (I am OK with seven segment...
  10. E

    Is while loop in vhdl synthesizable

    I am looking for VHDL based resources pls. Also any compilation of projects will be highly appreciated. Thanks.
  11. E

    Is while loop in vhdl synthesizable

    OK point accepted. Which free simulator do you advise. I have the free version of Xilinx ISE (latest). Also be kind enough to point me to any book/ site which has a collection of projects to start of with (in case I am unable to make the project, I will have a ready solution in hand). I was...
  12. E

    [SOLVED] While loop usage in vhdl is giving logical error

    sorry for the messed up description... i meant 3 iterations only instead of 3 clk cycles....!
  13. E

    [SOLVED] While loop usage in vhdl is giving logical error

    Hello, I was trying to make a 4 bit gray to binary code converter using while loop. It was giving me logical error in the waveform. During the first 2-3 clock pulses, the output bits were uninitialized. What can be the reason for it pls. The code is: ****************** library IEEE; use...
  14. E

    Is while loop in vhdl synthesizable

    Hello, is while loop in VHDL synthesizable. I was trying to implement a code and got the following error: It is a basic code: ************************** process(binary) variable i : integer := 0; begin gray(3) <= binary(3); while i < 3 loop gray(i) <= binary(i) xor binary(i-1); i := i+1...
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    Display different alphabets on 4 seven segment elements (connected in parallel)

    all the segments of the 4 units of 7 segment are connected in parallel viz segments dp of A,B,C and D units are connected in parallel, segments G in parallel and so on. I dont have architecture of the board. - - - Updated - - - OK thanks for the idea. Will try it out. BTW FvM, any reason...
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