[SOLVED] While loop usage in vhdl is giving logical error

[emmagood]

Hello,

I was trying to make a 4 bit gray to binary code converter using while loop. It was giving me logical error in the waveform. During the first 2-3 clock pulses, the output bits were uninitialized. What can be the reason for it pls.

The code is:

******************

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Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity gray2b is
    Port ( g : in  STD_LOGIC_VECTOR (3 downto 0);
           b : out  STD_LOGIC_VECTOR (3 downto 0));
end gtob1;
architecture Behavioral of gray2b is
signal  temp : std_logic_vector(3 downto 0);
begin
process(g)
variable i : integer ;
begin
i:=3;
temp(3) <= g(3);
while (i > 0) loop
temp(i-1) <= temp(i) xor g(i-1);
i:=i-1;
end loop;
--b<= temp;
end process;
b <= temp;
end Behavioral;

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******************




Thanks,
Emma Good.

 

[kommu4946]

You declared temp as a signal which will be updated after one delta cycle unlike variable .so declare temp as variable inside process and assign to output inside process.like this

architecture Behavioral of gray2b is



begin

process(g)

variable i : integer ;
variable temp : std_logic_vector(3 downto 0);
begin

i:=3;
temp(3) := g(3);

while (i > 0) loop

temp(i-1) := temp(i) xor g(i-1);
i:=i-1;

end loop;

b<= temp;

end process;


end Behavioral;

 

[TrickyDicky]

Your description of the problem is a little muddled. You talk about there being 3 clock pulses with unitialised signals, but I see no clocks in the design, and your code is not synchronous.

Also, although the code you have would be ok for synthesis, while loops are not recommended - you can only use them when the loop iterations are constant (as is the case here). You would be much better off sticking to for loops.

 

[emmagood]

sorry for the messed up description... i meant 3 iterations only instead of 3 clk cycles....!