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i have not experienced using assura yet but it is most likely referring to the distance between the P and N devices. try to increase the distance (20um as indicated in the error result) between the N and P device, as well as its taps (guardring) to remove the error.
all pads need ESD protection because they are directly connected to the external world. the power of the ESD may be connected to the power of the circuit it is protecting. but of course that depends to the ckt designer. the best solution is to tie the ESD devices to the most positive supply and...
if it is a high current circuit, transistors are large. split the transistor into several fingers and consider the width of the metals that deliver the current to the transistor. numbers of vias/contacts should also be taken into account so as not to suppress the desired current. ask the person...
if u only have one pin for vdd and a pin for vss, try to connect digital and analog power lines at the pad... this will reduce the possibility of digital blocks noise to mix with the analog signal because of bypass capacitors that are usually laid-out in the top-most hierarchy. isolate n wells...
Please help me provide the answers of the following.
How do you size NMOS and PMOS transistors to increase the threshold voltage?
Explain sizing of the inverter .
Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes (a) with increasing Vgs (b) with increasing transistor width (c)...
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