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Hi erikl,
Thanks for your reply. Actually, i had PI into full. The N-well was surrounding around it. I found out that my drc error was related to antenna diodes for the wells that is mandatory for the triple well process. Once i added those, the issue got fixed. I found the discussion in this...
Thanks for your reply dgnani. However, I have not shorted the P-well and the N-well ring. PI is tied to VSS and NW is connected to the vdd power rail. The inner most ring is the p-well ring which is connected to the Vss, the next ring which is nwell ring is connected to a different M1 power rail...
Hi,
I am designing a circuit that uses an isolated P-well in IBM 130 nm. To create the isolated Pwell, I used a PI layer and a N-well layer surrounding PI. Using a PI guard ring, each of the contacts(p+ contact for isolated p-well, n+ contact for n-well and p+ contact for the outside...
guys,
i have a doubt in image processing...suppose i have a circle in my image and i don't know what is the centre or its radius and given the fact that the circle can be located anywhere, can u give me some kind of algorithm through which i can determine the circle and its radius....
regards
Re: job interview questions
hi,
i agree with the answers...if in the second case, u think Bbar can't be given as such, u can use a mux to invert b..for that, give ' 1'(VDD) and '0'(GND) as the input to 0 & 1 pin of the MUX...now give b as the selection line..now when b is '1', then '0' is sent...
hi
actually i am do a hardware implementation of the ALU in fpga/asic..so, i am in search of algorithms which are efficient as well as implementable in hardware..
with regards
hi guys,
could u guys tell me which part of the flip flop circuit makes it edge sensitive???see,if it is level triggered,then it is because of the and gate used,here in flip how is it made edge sensitive??
with regards
Re: basic doubt!!
thanks for ur thoughts guys...so,i agree the increase in timing is a good gain...but,consider about the power?if number of flops is increased,then for the sake of timing,you are drastically increasing the switching power,the clock has to be routed to all those flops,increasing...
basic doubt!!
hi guys,
i have a fundamental doubt..i have a circuit which has some combinational elements and to reduce my critical path,i introduce a flip-flop at each intermediate stage so that the clock frequency of operation enormously shoots up..but,at the same time,if i increase the...
Re: floating point ALU
hi posotive_edge,
thanks for ur reply.. i have one more doubt regarding the FPU...what should be the exceptions that a FPU must give i.e i know nan,qnan & snan are a must..what others should i signal??and when exactly are qnan & snan signalled??
regards
floating point ALU
hi guys,
i have a serious doubt in representation of ieee 754 standard of represenation i.e. single precision std..assuming that i have a normalized form of representation(leading bit to be 1 always),with the exponent of 8 bits,mantissa of 23 bits,what is the maximum and...
hi guys,
suppose i am having 2 voice signals and i want to find the percentage of similarity between signals so that i can recognize voice..how should i go about it??what is the exact function??how can we achieve through the correlation ...
regards
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