[SOLVED] DRC problem in triple well process

[elecs_gene]

Hi,

I am designing a circuit that uses an isolated P-well in IBM 130 nm. To create the isolated Pwell, I used a PI layer and a N-well layer surrounding PI. Using a PI guard ring, each of the contacts(p+ contact for isolated p-well, n+ contact for n-well and p+ contact for the outside p-substrate), were connected to their respective power rails. Still, 2 DRC errros are seen =>

(i) Floating (NW not over T3) found! - NWell must be tied down by M1

(ii) Floating (PI not over NW) found! - PWell must be tied down by M1

Could anyone provide more light on the same? Would really appreciate any help. I have attached a snapshot of the circuit here for convenience.



Thanks

 

[dgnani]

it looks like you are showing PI ring connected to the NW ring which of course would be wrong, PI had to be tied to vss or an NFET source, NW had to be tied -usually- to vdd

 

[elecs_gene]

Thanks for your reply dgnani. However, I have not shorted the P-well and the N-well ring. PI is tied to VSS and NW is connected to the vdd power rail. The inner most ring is the p-well ring which is connected to the Vss, the next ring which is nwell ring is connected to a different M1 power rail which is vdd.

Thanks

 

[dgnani]

in your images both PI and NW rings are highlighted with the same red color... this means shorted in my cadence setup...

 

[elecs_gene]

Ok, I dont know how things got highlighted that way. I have attached the same layout without the highlight.

 

[erikl]

I am designing a circuit that uses an isolated P-well in IBM 130 nm. To create the isolated Pwell, I used a PI layer and a N-well layer surrounding PI.

I don't know this process technology. Does it own a global or local ("DNW", "Niso", s. examples below) buried N-layer which closes (short-circuits) the N-well ring? Otherwise you don't have an isolated P-well. If your process doesn't have this buried N-layer, you have to put the PI layer into a full -- not only surrounding -- N-well.

 

[elecs_gene]

Hi erikl,

Thanks for your reply. Actually, i had PI into full. The N-well was surrounding around it. I found out that my drc error was related to antenna diodes for the wells that is mandatory for the triple well process. Once i added those, the issue got fixed. I found the discussion in this thread useful.

Regards