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Recent content by ejean

  1. ejean

    Macro Cell vs Standard Cell

    RAM, ROM, ANALOG parts, etc--- MACRO CELLS USED for APR, with fixed horizontal and vertical pitches, with same height---STANDARD CELLS
  2. ejean

    structure of the power Mosfet

    You can reference Paradigm Shift in Planar Power MOSFET Technology h**p://powerelectronics.com/images/archive/311pet21.pdf & Power MOSFET in Detail (from To***ba) h**p://www.semicon.toshiba.co.jp/eng/prd/tr/doc/pdf/bde0034a_3.pdf
  3. ejean

    What is the future for CMOS Analog IC Designers ?

    Power management High Speed ADC RF
  4. ejean

    PCI bus and PCI-X bus - does it work?

    try this **broken link removed**
  5. ejean

    Converting a CDL netlist into a spice netlist

    cdl to spice I do it manually. Add head, include file, global variables. Kill * sign on useless lines. Add simulation status, power, etc. Good luck!
  6. ejean

    [SOLVED] who can recommend a book on asic design

    Principles of CMOS VLSI design, A system perspective Neil H.E. Weste and Kamran Eshraghian I think this is a very good refernece for IC design.
  7. ejean

    How to encrypt HDL design files with ability to synthesize ?

    DesinWare can produce BLOCK IP in encrypted format. If you want to provide your source code in encrypted format, you can choose pre-compiler base HDL simulator, these software can compile the original HDL code to it's "native-code". Modelsim, VCS, NC-verilog, SpeedSim, etc. can do this job.
  8. ejean

    Single File size exceed 2GB?

    Dear all, When I use tools to generate report file exceed 2GB, it makes core dump! Does Linux support a single file exceeds 2GB? What is the partition format I must choose? Thanks Ejean
  9. ejean

    Circuit Simulation for Full-Chip SoC Designs

    HSIM is the 'whole chip spice netlist simulator'. It speedup traditional spice 1,000~10,000 times(as the company announce), it's a 'fast spice simulator', in addition, it can read test vector(use it's tools covert from *.vcd ) to verify and simplify the test result in the digital parts. With the...
  10. ejean

    $ynplify ASIC vs. Design C0mpiler

    >aramis wrote: >I want to ask a question that is it >possible fo rme to convert using >synopsys DC into Synplify ASIC, >if the answaer is yes, what about >convert the DesignWare component?? >i have try using Synplify-ASIC, and >read the manual, but it doesn't >mention any about...
  11. ejean

    IC station "Asking"

    Try h*t*t*p://w*w*w.n*t*u.e*d*u.s*g/e*e*e/e*e*e*2/c*l*u*s*t*e*r*2_2/i*c/s*t*r*e*a*m_o*u*t/m*e*n*t*o*r%20GDS.pdf h*t*t*p://c*s*e*c.c*h*o*n*b*u*k.a*c.k*r/D*A*T*A/i*c*s*t*n_u*s*e*r.pdf h*t*t*p://w*w*w.e*l*e.u*r*i.e*d*u/R*e*s*e*a*r*c*h/c*h*e*r*r*y/m*e*n*t*o*r_t*u*t*o*r*i*a*l/i*c/ rm all *
  12. ejean

    Using DC to synthesis twice??

    h**p://w*w*w.i*e*o*r.b*e*r*k*e*l*e*y.e*d*u/~hochbaum/html/book-aanp.html NP-hard is not NP-complete, but it's 'hard' to solve. In other words, it's a very high BigO algorithm problem. To solve such kind of problem, we need some 'heuristic'. It need a 'seed', from the seed(an initial value), we...
  13. ejean

    Using DC to synthesis twice??

    almost EDA algorithms are 'NP hard' it means you may get different results in different machines, different platforms, different memory sizes, it is a 'relatively' optimized result, not 'absolutely'.
  14. ejean

    bind failed due to 98 - what is the message?

    bind failed due to 98 Dear all, What's matter with this message? bind failed due to 98: Address already in use Thanks for your any help BR, Ejean
  15. ejean

    New low-cost FPGA family...

    see the link below http://www.x!l!nx.com/prs_rls/silicon_spart/02140spartan_40mil.htm $2.55 for 5,000 system gates, $17.95 for the 300,000 system gates in volumes greater than 250,000 units. Regards, Ejean
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