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I usually do it by decreasing Vds and insuring that Vgb is high. This way I have both Vgs and Vgd relatively high, hence no pinching effect on either side of the channel. Unfortunately, in diode connected transistor you can not play with Vgd, so for current mirrors this will not work. You will...
Unfortunatelly, you can not avoid flicker noise in CMOS design. The source is imperfections in substrate-oxide region which cause random charge trapping and release of electrons. This is intrinsic to MOS transistor design so it can not be fully avoided, but it can be controlled to some point...
Re: IC5141
I found the same problem with 5033 and 5141, however this is on Fedroa Core 4. It seems to be problem with .cdsenv settings. Unfortunatelly I could not figure out yet which variable creates the problem.
Re: IC 5.1.41 platform
I am running it from Fedora Core 4 and Fedora Core 3. I have seen it run on Suse 9.3 and 10 (beta version). I am confident that you can install it on almost any Linux version today, since they are very similar, however, Cadence supports only RHEL 2.1 and 3.0.
In general...
Re: PLL
One of the best thing I found for PLL was spectreVerilog simulator included in cadence IC environment. But this is true only if you have complex PLL with large digital core. In such case you can replace analog components (VCO, PFD, Charge pump ....) with veriloga model, and use verilog...
spectre verilog
Hi,
I am trying to replace Verilog-XL with ncverilog in my mixed signal simulation due to lack of licence for Verilog-XL. Did anyone do this beofre?
I tried specifying ncverilog as default executable for digital part of simulation with +ncams option, however ncelab gives me...
procedure to design pll
1. Learn what each part of PLL does.
2. Get the specs (this will define topology and specs for each part of the loop)
3. System level (I recommend simulink)
4. Behavioural modeling (Either simulink or veriloga)
5. Replace veriloga models with actual schematics, in case...
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