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Recent content by eegchen

  1. E

    What's the relationship between PLL bandwidth and free-running frequency?

    Hi Biff44, Thanks. Could you give some more detail explanation why PLL become unstable for higher bandwidth?
  2. E

    Non-inverter OPAMP and Inverter OPAMP input impedance intuitive analysis

    Hi LvW, Thanks. The explanation is quite clearly.
  3. E

    Non-inverter OPAMP and Inverter OPAMP input impedance intuitive analysis

    Hi LvW, I agree with you . The input impedance is a small signal parameter. Do you know how to intuitively explain that ? Why Ri*(1+AB) not Ri/(1+AB)?
  4. E

    What's the relationship between PLL bandwidth and free-running frequency?

    hi, How to balance the PLL bandwidth with free-running frequency? I saw people said that usually PLL bandwidth is much less than free-running frequency, WHy? Thanks
  5. E

    Non-inverter OPAMP and Inverter OPAMP input impedance intuitive analysis

    Hi, Thank you for watching this post. For a simple feedback, like R1=R2=R, OPAMP's gain is A. Non-inverting feedback amplifier, the input impedance is (1+AB)*Ri, B is feedback factor. Inverting feed amplifier , the input impedance is R+R/(1+A) I can do some math to get the...
  6. E

    Help to analyze the Gain-by-2 switched cap based Amplifier

    Re: Help to analyze the Gain-by-2 switched cap based Amplifi So is it the reason of not symmetrical output swing ?
  7. E

    Help to analyze the Gain-by-2 switched cap based Amplifier

    Re: Help to analyze the Gain-by-2 switched cap based Amplifi thanks, That is what i am thinking, why it's not symmetrical. It's obvious caused by OTA. Is it because OTA has different discharge and charge cap? Best
  8. E

    Help to analyze the Gain-by-2 switched cap based Amplifier

    hi, I am designing a 1.5 bit Sub-ADC. The Gain-by-2 Amp is shown in the graph below. The sampling speed is 200MHz, Supply is 1.2. The waveform is only Gain-by-2 Amp result. the input is 300mvP-P. And the ideal output waveform should be 300mv--900mV and DAC output is fixed at 600mV. Gain of...
  9. E

    MOS as switch --hvt or lvt better?

    hi dick_freebird, That's very helpful. Thanks a lot.
  10. E

    bootstrapped switch quesion

    hi, I design a bootstrapped switch used in a simple sample/hold circuit( a bootstrapped switch with a cap load). The bootstrapped circuit and simulation result is in the following graph. In the simulation, the blue line is a ideal switch result. the red line is using a bootstrapped switch...
  11. E

    auto-zero comparator question?

    thanks. But should be V1P and V1n equal to Vcm ? best gang Added after 5 minutes: thanks. I still have a little confusion. If thing comes to V1p -V1n = (Vin+ - Vin-) + (Vc+ - Vc-) - Voffset Whey there are still the same? if we assume reference direction is fixed Best
  12. E

    MOS as switch --hvt or lvt better?

    yeah, just as a normal switch used in switch cap circuit like Sample/Hold. Added after 5 seconds: yeah, just as a normal switch used in switch cap circuit like Sample/Hold. Added after 2 minutes: Thanks. How can i know the requirements to define allowable leakage to not-fail the...
  13. E

    MOS as switch --hvt or lvt better?

    hi , I am designing a MOS switch. There are three types of threshold Voltage MOS, Low Vth, Normal Vth,and High Vth. As i know, low vth can run high speed but large leakage. High is low speed, small leakage. In the mos switch design, do you care about leakage ? Best Gang
  14. E

    auto-zero comparator question?

    hi backerShu, Thanks for your reply. What i don't understand is why Vin+ - Vc+ not Vin+ + Vc+? when i design charge pump, if you give a Vdd to Cap, it will boost the output. best Gang
  15. E

    auto-zero comparator question?

    hi, I read the auto-zero comparator, the first stage is to stage the offset error(top graph) And the second stage is to compare Vin and Vref, which will eliminate the error( low graph) I have question on the equation on second stage. Why (Vin+ - Vin-)- (Vc+ - Vc-)? Could you anyone help to...
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