Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Wow, thanks!
I did never understood this "negative" voltage... I always thought this should be a voltage below 0! :c)
And, thanks also for the correction on my messing up Q4/Q3.
Goulart
Hi, Keith!
I believe I understood your explanation. I'll see more on the "PN junction of the base-collector" on the net 'cause I admit it's not working as I thought it should. Of course I never expected transistors to work as a perfect switch; but, right now, I'm wondering how one could call...
Hi, Keith,
Thanks a lot for the nice and pronto replay!
I've been studying much at "Google school" and, according to what I've managed to learn, Q4, as a NPN, should be turned on with the absence (0V, or, with negative) voltage, not with +4.479V... This is the point I still didn't get.
I...
Hi, all !
I'm a beginner in electronic. I designed a digital clock and now I'm designing an UPS to keep it running even in mains failure. My question is: Why do I have the 4.479V at the upper side of Q3 when "Key=L" is open? Shouldn't I have there just a (residual?) voltage between 0V and...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
