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Recent content by eda_rattle

  1. E

    Definition of Generated clock in the following scenario ?

    What is the prb with Def2 ? This is correct as per definition.
  2. E

    Definition of Generated clock in the following scenario ?

    Hi, Two definitions given for two stage generated clocks ? Which one seems to be a better definition & WHY ? How does CTS tool build the clock tree DIFFERENTLY in two cases ? Definition 1 : create_clock -name SOURCE_CLK1 -period 1.0 [get_ports clk] create_generated_clock -source...
  3. E

    Clock Transition constraint v/s Data transition constraint

    Then why clock is kept at higher transition & not data ?
  4. E

    Clock Transition constraint v/s Data transition constraint

    Hi All, What are the reasons for keeping the max_transition at clock nets higher than data nets ? Only due to Xtalk ? Or there are other reasons also. For eg, in postcts stage if you have : set_max_transition 1.0 -clock_path [get_clocks X_CLK] set_max_transition 1.2 [get_designs *]...
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