Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
The above code just increase the pulse by one 'fast clock' because you are just introducing a flop and 'or'ing with the signal.
It definitely doesnt double the pulse width. Would work for cases where the width of the pulse is one fast clock...
Device Switching is fastest at low temperatures.
The timing analysis are done at extreme corners to ensure that they meet the timing specs.
a. Fastest case: Fast N and Fast P transistors, High Vdd, Low Temperature
b. Slowest Case: Slow N and Slow P transistors, low Vdd, High Temperature...
Search for Makefile.def in and around the location you found this Makefile.
Sometimes what is done is common portion in multiple Makefiles is put in a common file and is included using include statement.
So there is no definition like 'Makefile for SystemC'
There are good tutorials on Make...
If the input pulse doesnt repeat and this is being fed as clock to the synchronous counter then the output of the counter will be stuck.
This is about exactly doubling the input pulse width. What you have mentioned is a clock divider circuit.
According to me the right way is to design a...
Re: False Path
For any signal which enters a particular clock domain, timing check is done and error is reported if timing is not met. But some of these signals from design perspective you know that wouldnt affect your timeing. (For eg static register signals which are stable immediately after...
Due to speed requirements analog features are required in the design and a PHY layer is being employed. This is made as a hard macro. And to make it reusable a standard interface has been defined. So anybody who does a USB design can just do the non-PHY portion compliant to UTMI interface and...
Re: altera-quartus II tool
Altera Quartus is a FPGA design tool for the Altera series of FPGAs. If you are looking for ASIC as you mentioned in your post, you are looking at the wrong place.
Cheers,
eChipDesign.
=====================================================
eChip Design Labs
VLSI...
Re: Help from knowledged ppl on choosing VLSI specialization
hope you have the same impression of the course after completing it too :)
Cheers,
eChipDesign
=====================================================
eChip Design Labs
VLSI Training for Verilog and System Verilog
Nagercoil...
Creating an object of memory element and pushing it in a array has its own advantages if
a. you plan to implement a list of accesses to the same address.
(where in each address will store the history of accesses also)
i.e. scoreboarding in built in the memory.
b. If memory...
SV methodology , you should definitely go for OVM.
Cheers,
eChipDesign
=====================================================
eChip Design Labs
VLSI Training for Verilog and System Verilog
Nagercoil, TamilNadu
**broken link removed**
=====================================================
Whats is being done in the code is 'signed magnitude extension'. This is done by appending digits to the most significant side of the number.
If you want to increase the width then you should be extending the MSB instead of 7 (which is the MSB in this case).
Hi Jitendra,
Thanks for your feedback.
Once I have enough traffic on the website, I shall add more rooms specific to ASIC, FPGA, Design, verification, HVLs etc. For now since the visitor traffic is limited, we will continue with one common room.
Regards,
eChipDesign
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
