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Recent content by ece04

  1. E

    sar adc design in cadence virtuoso

    the output of the comparator is a digital pulse.The problem is with reset pin input?
  2. E

    sar adc design in cadence virtuoso

    giving negative pulse to reset is it ok.or wht should i give as input to reset clk and input?
  3. E

    sar adc design in cadence virtuoso

    I am trying to make an sar adc.for sar logic i am using aynchronous d flipflop.i am using following circuit https://obrazki.elektroda.pl/7371221100_1363591157.png problem is tht i am not getting output correct.I am giving negatve going pulse to reset and posive pulse to clk and input .all...
  4. E

    ring counter using d flipflop

    input to clr should be pulse or constant voltage?I mean vpulse or vdc?
  5. E

    ring counter using d flipflop

    thank you for reply.I have one more question what should i give as input to reset and clr .I was giving input vdc with 2v and input for vdd is 2.5 v.Is it ok?
  6. E

    ring counter using d flipflop

    I am trying t make ring counter in cadence virtuoso using d flipflop.I need to know wht should we do with unconnected pins like clr pin of first flip flop and set pins of rest flipflop. <a title="ringcounter.png" href="http://obrazki.elektroda.pl/6539339700_1363354309.png"><img...
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