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Thanks, FVM. Do you have better idea to drain the cap faster than putting a parallel resistor?
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Thanks, FVM. Do you have better idea to drain the cap faster than putting a parallel resistor?
Thanks for the reply, FVM.
Below is the actual circuit. The difference is that I added the reversed protection and using 2 pass fets.
Can't figure out what's wrong. Besides adding the drain resistor, any idea to discharge the 47nF faster?
Thanks.
Barry, thanks for the clarification.
So can i say the gate pull up current is purely from the chargepump as shown in the block diagram.
The problem is that i has a 28V powered board using this chip to limit the inrush current. I put a 47nF to ground at the gate to slow down the turn on.
The...
Hi, all,
I have difficulty to understand one of the spec in LT4356 datasheet.
I had thought this gate pin pull up current is to source current to charge the mosfet parasitic capacitance and any external capacitor on the gate.
This has to be positive, right?
And this to be fairly large, right...
I understand the issue of tuning tolerance that may not give me an exact center frequency.
But lets say this is being taken care of. They are both nicely matched.
Are they considered identical at the starting temperature where the tuning takes place?
I have 2 crystals on hand now.
Crystal 1...
My thinking is that since matching is a norm to make every part starting with 0 ppm at room temp, why the supplier bothers to put the frequency tolerance into the spec then.
After both crystals go through the matching exercise at room temp, both crystal operates at their center frequency.
Are both parts equal in performance under room temp?
And i can just focus on the frequency stability and aging spec in selecting the suitable crystal?
hi,
My understanding is that 'temperature' drift is classified as frequency stability and 'time' drift is as aging.
Frequency tolerance is the initial tolerance.
hi, all,
I am a bit confused by the concept of frequency tolerance of a quartz crystal.
I can always carry out a load capacitance matching exercise to make sure the crystal is working at its center frequency, right?
After matching, the crystal is working at 0 ppm?
Then how does the frequency...
hi,
If i have to stick with this PWM controller, what are the improvements i can make to boost its performance?
I have an separate 5V power path for an MCU. The MCU can fulfill the UVLO and SS function. For the totem pole, no much i can do, right?
It is better to get a FET instead of BJT based...
Looking at the PWM controller datasheet, it is fairly complete to me. Error amp, oscillator, fet driver, etc. I do not need those soft start, UVLO features anyway.
Anything i have overlooked?
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