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LT4356 gate pull up current specification

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dyunasing

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Hi, all,
I have difficulty to understand one of the spec in LT4356 datasheet.
1623643242899.png

I had thought this gate pin pull up current is to source current to charge the mosfet parasitic capacitance and any external capacitor on the gate.
This has to be positive, right?
And this to be fairly large, right, as peak current is concerned?
Could anyone help to enlighten me? Thank you.

Dyu
 

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The Negative Sign indicates current is flowing out of the device. It does not have to be large because the gate voltage is normally high, it gets pulled low during an overvoltage event.
 
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Barry, thanks for the clarification.
So can i say the gate pull up current is purely from the chargepump as shown in the block diagram.
1623650713761.png


The problem is that i has a 28V powered board using this chip to limit the inrush current. I put a 47nF to ground at the gate to slow down the turn on.
The inrush limiting seems to work only on the first power up. Then I realized the 47nF is taking very long (>10s) to discharge.
When I powered on/off the supply repeatedly, there was a brief period the gate is pre-biased by the 47nF stored charges, which led to the early turn on of the passing mosfet.
I tried to put a parallel resistor across the cap to discharge during OFF state. But when I put a 2Mega ohm across and turned on, the chip was damaged.
I am just thinking could the 2Mohm overloading the current source.
Any thoughts?
Thanks.

Dyu
 

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Unlikely that the 2 Mohm resistor causes damage of the chip, the current source output is regularly pulled down in operation. I can just guess that your setup is somehow different from the suggested application circuit.
 
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Thanks for the reply, FVM.
Below is the actual circuit. The difference is that I added the reversed protection and using 2 pass fets.
Can't figure out what's wrong. Besides adding the drain resistor, any idea to discharge the 47nF faster?
Thanks.

1623656399089.png
 

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The reverse protection circuit looks wrong. The transistor isn't turned on in normal operation and doesn't protect the controller against supply voltage reversal.

Either use an industry standard PMOS reverse protection, or a simple input diode.
 

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For the reversed protection, I am following the application circuit, anyway.
1623658922887.png
 

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O.K., I see that LT4356 has internal reversal protection for the sense pins. The "-80V protection" scheme is better though. Also protection FET is turned on by the charge pump voltage. Sorry for confusion.

Nevertheless it should be no problem to force 47 nF discharge during power off.
 

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Thanks, FVM. Do you have better idea to drain the cap faster than putting a parallel resistor?
--- Updated ---

Thanks, FVM. Do you have better idea to drain the cap faster than putting a parallel resistor?
 

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