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Re: multiplier
the best way is to instantiate a multiplier if you are using fpga（c=a*b;) .
If you want to implement ASIC,you can use booth arithmetic and 4-2 compressor.
synchronous: always@(posedge clk )
begin
if(rst==0) ......
else ..............
end
asynchronous:always@(posedge clk or negedge rst)
I think synchronous is better in...
How can I implement a leading zero detector?
If x+y=z(they are all 50bit),and I want to know the leading zero of z only use x and y,so how can I do that?
Thx!
absolute value in verilog
Tthere is no power opertor or square root operation in verilog HDL. square root operation is difficult to design and cost a lot of resources.
the absolute value(b=|a|):
reg a [31:0];
reg b [31:0];
always@(*)
begin
if (a[31]==1'b1)
b[31:0]={1'b1,a[30:0]};
else b...
Re: clock dependent counter
U can use a reg[2:0] . 000\001\011\010\110\111\101 to implement the counter.It can be made as a FSM.
I think the system clk is better.
Re: SYSTEMC
I think it's a good idea,and I know that somebody did this before.
I think sc2v is not very good,so I always transform by myself.
I have the e-book of systemC primer,and who want it can contact me.
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