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I would do a only-R extraction and follow the signal node by node to identify which R is causing the problem. As ThisIsNotSam mentioned, the problem might be due to an extraction error, a non realistic R value or a wrong node connection .. SRAMs are always touchy. That is why checking the...
Hi,
If the techology in question is FD-SOI, the hybrid layer represents bulk opening areas on SOI subsrate, thus allowing you to build structures as conventional CMOS without SOI, or PTAP/NTAP connections to supply wells of SOI devices.
How do you do connections on the top level ? If these ground signals are supposed to be same, and connected on the top, then there should be only one signal name ( one pin !)
However be careful, if AVSS is supposed to be an "isolated ground", in this case you should use guard-ring.
If one...
Hi allen,
I am not familiar with TSMC 65nm PD, but with I/O circuits in general so my answer might or might not be heplful/
1 - Analog I/O IP should come with a documentation in the PDK, in which AC/DC switching characteristics, min and max operating voltage and frequency should be...
Hi people,
I am currently interested on cell characterization methodologies and looking for ".lib" file creation. I have a little confusion on three state cells.
Let's consider a three-stete buffer cell, I see on several ".lib" files rise and fall transition time w.r.t enable pin. Rise/fall...
CMOS thermal sensor circuit is another application in which temperature independent references might be used depending on the used transducer technique.
PMOS mobility is lower than the NMOS therefore more width is required to reach similar amount of saturation current as an NMOS. This is valid for the case (and this is the most common case) where the designer wants balanced pull-up and pull-down currents.
Hi,
I am simulating IBIS model using Mentor Graphic's SPICE simulator ELDO. While testing differential buffers with differential termination at input side, I notice that "R Series" model defined with [Series Pin Mapping] is not detected in this simulator. The simulation behaves like there is no...
Both documentation and SPICE simulations.. In general the Design Kits come with all kind of documentation, not only DRM. Based on what you are looking for, one of these documents might be the one you are searching for.
I start by investigating mos characteristics, pmos-nmos Ion ratios, leakage, gate capacitance, temperature variations etc .So I can think about what will be the impact on my design and modifications that has to be done.
Substrate isolation is done by using triple well layer (usually named deep-n-well), a deep n-well layer allows you to create isolated pwell between nwells. But If the cmos process you are using does not have triple well support then you cannot isolate pwell's therefore you cannot have separate...
Re: Top level IO cells connection ( multiple IO voltages and global source use ) and
In a bi-directional I/O pad design, I/O signal should go first through ESD protection before reaching any MOS gate, so that the MOS gate won't suffer any oxide breakdown. Therefore a signal which is not yet...
You may try to run SOACHECK if your simulator supports that (assuming TSMC models have their SOAs defined). This can tell at least if the operating modes are accurately modeled.
Are you sure that LVS options in your PEX script (or config file) are same with the ones when you do only LVS ? My opinion is that, for the same layout, if LVS works fine and LVS within PEX is not, this can be only due to the difference in the given options ...
Also a layout which is LVS...
Re: Top level IO cells connection ( multiple IO voltages and global source use ) and
ESD charge should not attack the gate of a MOS. Probably what is happening is that the MOS model behaves out of specification and for whatever reason and you see a discharge, which is a "false true". The...
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