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dolby.yang

Recent content by dolby.yang

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Need the verilog code can read DS1820

ds1820 verilog who can share the verilog code that control DS1820. Need the verilog code can read DS1820. Thanks !
- dolby.yang
- Thread
- Sep 3, 2009
- Replies: 0
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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I2C master controller problme

Hi, Currently i want do a I2C master controller for AT24C512B eeprom，i searched the ip core for I2C on net, that is not fit for 24C512b ,because 24C512b random read operation need 2 word address following the device address ,i saw the i2c core on net most of them are one word address for...
- dolby.yang
- Thread
- Jan 10, 2009
- Replies: 2
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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How to define the attribute in synplify !

synplify synkeep Thanks your reply, i have put the syn_keep after the signal define,this attribution seams no any use for this issue . wire wire_i_want to keep /*sythesis syn_keep =1 */;
- dolby.yang
- Post #4
- Dec 25, 2008
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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How to define the attribute in synplify !

synplify syn_keep who can support this issue ?
- dolby.yang
- Post #2
- Dec 19, 2008
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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How to define the attribute in synplify !

synplify define How to define the attribute that keep the synplify change the signal name when it do synthesis? syn_keep and syn_preserve seams have no this funciton ? thanks !
- dolby.yang
- Thread
- Dec 16, 2008
- Replies: 3
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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what is the FPGA I/O status before configuration ?

Thx. i got it !
- dolby.yang
- Post #3
- Aug 4, 2008
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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what is the FPGA I/O status before configuration ?

what is the FPGA I/O status before configuration after power up? Tks!
- dolby.yang
- Thread
- Aug 2, 2008
- Replies: 2
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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about the lattice ip core simulation !

thanks for your reply!
- dolby.yang
- Post #3
- May 17, 2008
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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about the lattice ip core simulation !

I am using the lattice FPGA. I use IPexpress generated a CIC ip core. i instantiated this ip core in my top design. here i have a problem . how to use this ip core's behavior model in simulaton ？ when i add this behavior module file to my simulation project and compile it . i will meet many...
- dolby.yang
- Thread
- May 17, 2008
- Replies: 2
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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how to interface fpga board to PC

you can use PCI interface . do you have PCI interface in your FPGA or board?
- dolby.yang
- Post #3
- Jul 13, 2007
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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Which VHDL/Verilog Editor is the best ?

verilog code editor i think here is not a best,but a more suit . i like vi
- dolby.yang
- Post #13
- May 22, 2007
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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A doubt on DDR SDRAM latency..................

hi , the cl=5 means the required cycle number that the first bit data come out after u issued read comand.
- dolby.yang
- Post #2
- Dec 13, 2006
- Forum: ASIC Design Methodologies and Tools (Digital)
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Problem with installing Synplify on Windows XP

Re: Installing Synplify can u tell us your problem's detail when u install this software?
- dolby.yang
- Post #2
- Nov 30, 2006
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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Can you implement image processing to Spartan-3 starter kit?

Re: Spartan -3 spartan 3 maybe not enough for your project!
- dolby.yang
- Post #3
- Jan 6, 2006
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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Suggestion on FPGA and DSP starter materials

Re: FPGA starter for beginner,www.xilinx.com www.altera.com will be suit for you and us!
- dolby.yang
- Post #4
- Jan 6, 2006
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design

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dolby.yang

Welcome to EDAboard.com

Recent content by dolby.yang

Need the verilog code can read DS1820

I2C master controller problme

How to define the attribute in synplify !

How to define the attribute in synplify !

How to define the attribute in synplify !

what is the FPGA I/O status before configuration ?

what is the FPGA I/O status before configuration ?

about the lattice ip core simulation !

about the lattice ip core simulation !

how to interface fpga board to PC

Which VHDL/Verilog Editor is the best ?

A doubt on DDR SDRAM latency..................

Problem with installing Synplify on Windows XP

Can you implement image processing to Spartan-3 starter kit?

Suggestion on FPGA and DSP starter materials

Part and Inventory Search

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