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Recent content by dillikumar406

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    How do you find the damping ratio of this feedback system?

    sqrt(5/2). no need of input response because c(s)/r(s) = g(s)/(1+g(s)h(s))
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    Width mismatch error in VHDL..!!!

    for demux you shoud have one input and many output. but in your code you defined many inputs
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    power amplifiers and classes of amplifier

    you can try the book "elctronic circuit analysis" by lal kishore
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    [SOLVED] Why does CMOS logic give complementary output?

    if you go through the operation of the elements in the design you can easily understand why it is working like. it is because of the opposite elements used in the design (pmos,nmos)
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    verilog to vhdl conversion?????

    registers are nothing but wires but we use them in behavioral description only
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    verilog to vhdl conversion?????

    in vhdl signals are the intermediate connections between the gates and modules. these signals are defined as wires in verilog
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    vlsi chip designing.....

    in verilog we can add delay by using # symbol in locking and non-blocking assignments. you can find them if you go through verilog coding books
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    [MOVED] vlsi chip designing.....

    Re: vlsi chip designing..... we can design buffer without using clock also. i dont know modelsim simulator
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    VLSI simulation tool.

    choose the software according to your project. xilinx is used for coding, but for simulating circuits and to generate schematic it is not suitable. for circuit designing you can use hspice, mentor graphics..
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    [MOVED] vlsi chip designing.....

    Re: vlsi chip designing..... buffer can be constructed as a cacaded version of two inverters. latch is a memory element which adds some amount of delay to the output and also requires clock.
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    [SOLVED] purpose of Resistors and Capacitors in CMOS inverter as a small signal amplifier

    capacitors are used to block dc and allow ac, it acts as a filtering agent.resistors are used as conducting ad discharging element to discharge the excess amount of heat generated during circuit operation towards ground thereby protecting the circuit.
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    help me to get IEEE research papers

    you can download them by getting membership in ieee.
  13. D

    [MOVED] Help with simulating inverter

    connect pmos in pull up section and nmos in pull down section.while pmos source is connected to Vdd and nmos source is connected to ground.

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