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Digit0001

Recent content by Digit0001

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Programming design to FPGRA board Problem

The two files i an missing is a PROM and CPLD file, so how do i obtain them?
- Digit0001
- Post #2
- Oct 31, 2011
- Forum: Microcontrollers
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Programming design to FPGRA board Problem

Hi My problem is when i download the programm via impact i only get the topbit however i am meant to have another file as well. Can somone tell me the solution to this? The attached pdf has the screenshots of the problem i just described. NOTE the board i am using is Spartan 3E P.S Mods...
- Digit0001
- Thread
- Oct 31, 2011
- Replies: 1
- Forum: Microcontrollers
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Creating a Bouncing Ball program in C on a FPGRA board

Creating a Bouncing Ball program in C on a FPGA board Hi I have having trouble on how would you make the ball move i know you would need to have something like this to move the ball, but how does this work. x = x + dx and y = y + dy Hope someone can help me P.S
- Digit0001
- Thread
- May 1, 2011
- Replies: 1
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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Need Help on combining two processes in VHDL

The temp is used to save the last count value. The purpose is because i am measuring the period of the pulse width.
- Digit0001
- Post #8
- Apr 7, 2011
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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Need Help on combining two processes in VHDL

i have a problem when i simulate the code. The modified code does not change states and the counter does not count. This is the code i have: this includes what i have in simulator and implementation.
- Digit0001
- Post #6
- Apr 7, 2011
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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Need Help on combining two processes in VHDL

thanks, i understand now
- Digit0001
- Post #5
- Apr 6, 2011
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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Need Help on combining two processes in VHDL

Hi Can someone suggest how would i combine the following code into one process? The code is made up of a counter and a state machine which i want to make as one process. The problem i am having at the moment is the count will not work because it conflicts, hence i want to make it in one...
- Digit0001
- Thread
- Apr 6, 2011
- Replies: 7
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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Problem with 4-bit ALU Design

lets say i still want to keep the operation in tack, would i still require two case statements for the tables
- Digit0001
- Post #3
- Feb 20, 2011
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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Problem with 4-bit ALU Design

Hi i am having trouble designing a truth table for the 4-bit ALU. The document details the specifications: My problem is how would i combine the arithmetic table with the logic table into one table? The only way i can think of is do it in separate tables This is what i have in code...
- Digit0001
- Thread
- Feb 19, 2011
- Replies: 3
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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The Difference between the two processes

Hi Can someone tell me the difference between the two processes? process(A) variable start : bit :='0'; begin Start :='0'; For i in 0 to 3 loop start := start or A(i); end loop; x <= Start; end process; process(A) variable start : bit_vector(4 downto 0); begin...
- Digit0001
- Thread
- Feb 15, 2011
- Replies: 2
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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variable question in VHDL

ok i understand now ---------- Post added at 10:35 ---------- Previous post was at 10:31 ---------- however in general cases would this happen regularly? I assume most people when designing would not want a code to wait four clock cycles to update a signal.
- Digit0001
- Post #4
- Feb 15, 2011
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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variable question in VHDL

Hi Can someone tell me if this is true, Variables declared inside a clocked process are treated as signals for the purpose of synthesis. P.S
- Digit0001
- Thread
- Feb 15, 2011
- Replies: 4
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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[SOLVED] synchronous 4 bit counter problem

solved my problem, something with my coding.
- Digit0001
- Post #5
- Feb 13, 2011
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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[SOLVED] Quick VHDL coding question

yeh i think so. unfortunately i don't have any answers to this question so i cannot check if it is correct.
- Digit0001
- Post #19
- Feb 13, 2011
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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[SOLVED] synchronous 4 bit counter problem

i have tried it again, can someone tell me where is my mistake, because when i simulate it doesn't give me an output for Q. architecture Behavioral of ques4 is signal count : std_logic_vector(3 downto 0); signal tCout : std_logic; begin process(clk,clear,count,P,T,Load) begin if(clear =...
- Digit0001
- Post #3
- Feb 12, 2011
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design

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Digit0001

Welcome to EDAboard.com

Recent content by Digit0001

Programming design to FPGRA board Problem

Programming design to FPGRA board Problem

Creating a Bouncing Ball program in C on a FPGRA board

Need Help on combining two processes in VHDL

Need Help on combining two processes in VHDL

Need Help on combining two processes in VHDL

Need Help on combining two processes in VHDL

Problem with 4-bit ALU Design

Problem with 4-bit ALU Design

The Difference between the two processes

variable question in VHDL

variable question in VHDL

[SOLVED] synchronous 4 bit counter problem

[SOLVED] Quick VHDL coding question

[SOLVED] synchronous 4 bit counter problem

Part and Inventory Search

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