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Hi, supposed PA amplifies one CW, in these two conditions, may I ask which one has the highest 2nd harmonics?
A. center frequency =2.4GHz, Bandwidth=100MHz, Power spectrum density(PSD)=2W/MHz
B. center frequency =2.4GHz, Bandwidth=200MHz, Power spectrum density(PSD)=1W/MHz
I think A should...
Hi, I don't know what's complementary . To be honest, this is the first time I heard this. Could you please explain it more? I use DCVSL structure, similar to this paper...
Hi, all
I'm designing a differential ring oscillator. I want to simulate the influence of supply voltage noise on phase noise.
I use "Number of noise/freq pairs" in vdc to generate noise, as Figure shows. I compare the phase noise with noise (Number of noise =2) and without noise (Number of...
Hi, all
I have a question need your help. Thanks in advance. I want to design a current source(CS) with the below requirement in 180nM.
1. Voltage control and current have the linear relationship.
2. Current mirror can supply enough current. It means if I let MOS W/L low enough to let CS work...
Hi, all
I wanna add a clock signal using "vpulse" in vco circuit. When I run 'pss'. It will show this error.
It seems oscillators circuit cannot work together with clock signal.
Do you know how to fix it? Thanks
Hi Brian， this is a differential ring oscillator. I want to reduce phase noise further. Because the noise of supply voltage can be counted into 1/f noise I think. As I think, because the supply noise on two output are coherent, I think maybe I can use this way to cancel supply noise.
Really? But balun needs inductors which has big loss in low frequency.
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My idea is: suppose the noise from Vdd(Vdd is supply voltage. The noise should be common mode) can affect outputPlus and outputMinus signal. If I want to cancel supply noise. There are two ways:
1. I...
Hi all, could you please give me some hint?
I'd like to realise subtraction on differential signals. My purpose is to cancel common mode signal and to amplify differential mode signal.
How to make subtraction on voltage?
1. Because the frequency is lower than 100Mhz, I cannot use inductors...
Suppose I don't know this is low-pass or high-pass filter in advance.
If I don't not use the Av formula with j inside(Because I really think it's complex) to calculate the pole or zero, is there some faster method to know whether this is a zero but not a pole?
In my opinion, C should connect...
Hi,all
I want to design differential ring oscillator. I want to know how to determine the aspect ratio of all nmos and pmos transistor of the delay cell? What is the design procedure of differential ring oscillator?
I check many papers but cannot find the step-by-step description.
Thanks in...
In this paper, there are two sentences:
1. The maximum voltage observed at the gate of M9 is Vg(max)=Vc2-Vtn,. As Vc2 increases the average, gate voltage of the PMOS transistors increases.
2. Large M6 and M10 increases the Vg(max) of M9 and MI0 and hence extends the tuning range.
I'm confused...
Thanks for the picture. Could you please expain more about "the choice of the common PN reference point of -120 dBc/Hz @ 10 MHz"? And what's the reason that lower 1/f^3 corner frequency has lower phase noise?
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In this picture, if I reduce 1/f noise. the corner frequency...
Hi, I don't understand: Why accumulated magnetic flux equals to high impedance but not low impedance?
based on your example:
--> for commom mode (noise) both path´s inductance are in parallel, the total inductance should be 1mH/2=0.5mH. Why total inductance is 2mH.
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