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Thanks Klaus.
From the Silicon testing, looks like the the reg/Q is not getting asserted. We can only give one posedge to the register during the entire test. We cannot provide a negedge and toggle again. Will that be an issue for a flop , blocking from setting the value?
Thanks
Hi,
We have a positive edge triggered register (flip flop) in the design. With a design limitation, we could only give one positive edge to the register/CK and unable to launch a successive negetive edge. Will this cause any issues with the register behavior at silicon?
Only single edge...
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