A register that only gets a positive edge

[DFT Engineer]

Hi,

We have a positive edge triggered register (flip flop) in the design. With a design limitation, we could only give one positive edge to the register/CK and unable to launch a successive negetive edge. Will this cause any issues with the register behavior at silicon?
Only single edge possible to provide with the deisgn limitation. Reset also cannot be applier as it is connected to power-on-reset. The gate level simulation shows a Q transition from 0->1. Will the silicon behaves the same or a complete cycle or the successive negedge is mandatory?

Thanks

 

[KlausST]

Hi,

Nothing happens on the falling edge. In doubt read the documentation.

I can not remember to have read about a a falling edge.

What are your concerns?

Klaus

 

[DFT Engineer]

Hi,

Nothing happens on the falling edge. In doubt read the documentation.

I can not remember to have read about a a falling edge.

What are your concerns?

Klaus

Thanks Klaus.
From the Silicon testing, looks like the the reg/Q is not getting asserted. We can only give one posedge to the register during the entire test. We cannot provide a negedge and toggle again. Will that be an issue for a flop , blocking from setting the value?

Thanks

 

[FvM]

Flops with limited functionality (set once, never reset) can be commonly found in reset synchronizers. Obviously you can only test the implemented functionality, but why would you doubt its correct function?