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Re: ic5141 problem in fc6:symbol errno, version GLIBC_2.0...
thank you for your help, napalmer.
now i have installed the ic5141 on rhel4, and they worked perfectly.
thanks for your help sandeep_torgal and Troy.
in the summary purpose item , what's the difference of "drawing" and "net" ?
i found that many "drawing" layers are not included in the assura extracted view, but included in the diva extracted view.
Re: DIVA
are you using a pdk ?
if u are using a pdk, there should be divaDRC.rul , divaLVS.rul and divaEXT.rul in the pdk. you can use these files for your extraction, just like the assura.
an instance of an undefined model pch3
thanks for your reply, Johnson.
i'm using chrt 0.18 rf pdk.
and i can find the model of dnwpw_1p8 in the pdk models. but there is no model for dnwpw.
how could this dnwpw be produced ,since there's no model for it ?
is an instance of an undefined model
when i tried to make post-simulation using specte simulator with the extracted view (produced in DIVA), i got some errors in the spectre.out :
Error found by spectre in `stage1_rfpdk_sym_fordiva_extracted', during circuit
read-in.
input.scs: +8...
Re: where the termiinal "DN" and "SUB" c
thx for ur reply, Raduga.
yes, i connected the substrate to the gnd (the most negative voltage in the circuit) and n-well to the most positive voltage. but there were error tips when i complete the simulation.
the rf mos is deep nwell process and has six terminals. where the termiinal "DN" and "SUB" connect to ?
when i connect "DN" to VDD, and "SUB" to the GND , some errors like "plus: can't handle (nil nil)" appear in the schematic editor.
how to deal with this problem?
thank you in advance.
rcxfs assura
why some layers missed in the extracted view ?
i put a MOS with it's d and s connected to ground, then layout, drc, lvs, and finally extracted.
but some layers missed in the extracted view of av_extracted, such as the poly layer.
i attached those snapshots in this post.
at the...
I run "Design synthesis -->Layout XL" in virtuoso schematic editor , then I run "Placer" or "Export to Router",there will be warnings in CIW,says:
......
\o Export from DFII: Starting export.
\o Exporting "Inverter inv_sym layout" from DFII...
\o Exporting version 11.0.9 syntax from...
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